The present invention relates generally to driving circuits for capacitive load, and more particularly to a system and method for achieving fast switching of analog voltages on a large capacitive load.
A conventional driving circuit or driver for driving a capacitive load typically consists of a signal input, a signal output and an amplifier or an analog voltage buffer to drive the load between two or more voltages. Two important properties of a buffer are power consumption and response time, which is the time required for the buffer to reach a specified output following the application of a specified input under specified operating conditions. Generally, these two properties cannot be optimized simultaneously. This is because improving response time means increasing unity gain frequency and slew rate, the ability of an amplifier to reflect a change in the input in the output quickly, both of which require increasing bias current of the buffer. Thus, reducing response time requires increasing power consumption, and reducing power consumption results in a increase in response time.
There are prior art designs for buffers that dynamically increase the bias current to improve the slew rate only when needed, thereby improving the response time while limiting the increase in power consumption. However, the design of such a buffer is complicated and exhibits several undesirable characteristics such as instability. These dynamic buffers also produce significant noise on supply lines during voltage transitions when the needed charge is drawn quickly, thereby requiring the addition of complex and often costly filters.
The above shortcomings of conventional driver circuits are particularly a problem for driving circuits used, for example, to drive floating gates of FETs (Field Effect Transistors) used in semiconductor devices such as storage elements or cells in non-volatile memory systems, such as electrically erasable programable read-only memory (EEPROM) or flash memory. The floating gate in an FET is not directly connected to the rest of the device and thus appears to the driving circuit as a purely capacitive load. This capacitive load can be quite large since a large number of storage elements in the non-volatile memory system, typically from 16 thousand to 10 million storage elements depending on the size of the memory, must be switched simultaneously between a programming voltage and a verify voltage. A programming voltage is a voltage applied to store information in the storage element as a charge on the floating gate. A verify voltage is used to determine if the storage element has stored a proper amount of charge and therefore the information. The transition between programming voltage and verify voltage and vice versa must be fast to achieve satisfactory write-performance. However, such driver circuits are frequently used in portable, battery operated devices in which the available power is limited and therefore must be conserved. Morever, the power for the driver circuit is usually supplied by an on-chip high-voltage-pump. Because both the generation and consumption of power produce heat that must be dissipated for the devices on the chip to function properly, conserving power is again necessary. Thus, increasing the bias current to improve the response time in the buffer is generally not desirable.
Accordingly, there is a need for a driving circuit for driving a capacitive load that provides an improved response time to drive the load between two or more voltages without increasing power consumption of a buffer in the driving circuit.
In one aspect, the present invention provides a driver for driving a capacitive load, the driver having a load buffer with an input for receiving an input voltage (VIN), and an output for coupling an output voltage (VOUT) to the capacitive load. The load buffer is configured to drive VOUT between a first voltage level (V1) and a second, higher voltage level (V2) in response to a change in VIN. The driver further includes a reserve circuit configured to reduce the time for VOUT to transition between V1, and V2. The reserve circuit has a reserve capacitor or capacitor, a reserve buffer, a switch for coupling the reserve capacitor to the capacitive load and a controller for opening and closing the switch. The reserve buffer has an input for receiving an input voltage (VRESxe2x80x94IN), and an output for coupling an output voltage (VRESxe2x80x94OUT) to the reserve capacitor to charge the capacitor. The controller is configured to operate the switch to couple the reserve capacitor to the capacitive load when VOUT is being driven between V1 and V2. Generally, the controller is coupled to the input of the load buffer, and is configured to operate the switch when a change in VIN is required.
In one embodiment, the reserve buffer includes a negative feedback loop to provide a gain that is substantially equal to unity. The reserve buffer is configured so that when VIN equals V1, VRESxe2x80x94IN has a steady state value of V2+a, and when VIN equals V2, VRESxe2x80x94IN has a steady state value of V1xe2x88x92a, where a equals (V2xe2x88x92V1)CLOAD/CRES, and where CLOAD is the capacitance of the capacitive load and CRES is the capacitance of the reserve capacitor.
In another embodiment, the driver includes a second switch for electrically isolating the capacitive load from the output of the load buffer. The second switch is operated by the controller to open when VOUT is being driven between V1 and V2. Desirably, the second switch is operated by the controller to simultaneously open when the first switch is closed and to close when the first switch is opened.
In yet another embodiment, the reserve circuit includes first and second reserves capacitors, CRESxe2x80x94A and CRESxe2x80x94B, and first and second reserve buffers having inputs adapted to receive first and second input voltages, VRESxe2x80x94INxe2x80x94A and VRESxe2x80x94INxe2x80x94B respectively, and outputs adapted to couple first and second output voltage, VRESxe2x80x94OUTxe2x80x94A and VRESxe2x80x94OUTxe2x80x94B respectively, to charge CRESxe2x80x94A and CRESxe2x80x94B. A single pole, double throw switch capable of alternately coupling CRESxe2x80x94A and CRESxe2x80x94B to the capacitive load, is operated by a controller to alternately couple CRESxe2x80x94A and CRESxe2x80x94B to the capacitive load when VOUT is being driven between V1 and V2.
The driver of the present invention is particularly useful in non-volatile memory systems such as a flash memory having a number of storage elements or cells with a number of Field Effect Transistors (FETs), each of the FETs having a gate coupled to the driver, and the driver configured to periodically drive the gates between a programming-voltage and a verify-voltage. Generally, the non-volatile memory system further includes a high-voltage-pump to supply voltage to both the load buffer and the reserve buffer. In one version of this embodiment, the storage elements, the driver and the high-voltage-pump are fabricated on a single semiconductor substrate.
In another aspect, a method is provided for operating the driver of the present invention. In the method, when VIN changes from V1 to V2 or from V2 to V1, the load buffer is then operated to drive VOUT from V1 to V2 or from V2 to V1 in response to the change in VIN. At the same time, or shortly thereafter, the switch is closed to couple the reserve capacitor to the capacitive load, thereby reducing the time necessary for the capacitive load to transition between V1 and V2. Generally, the step of closing the switch involves closing the switch only briefly until VOUT has reached V1 or V2.
In one embodiment, as described above, the reserve circuit further includes a reserve buffer coupled to the reserve capacitor, and the method further includes the steps of charging the reserve capacitor to a voltage level (VRESxe2x80x94OUT) using the reserve buffer, and discharging the reserve capacitor into the capacitive load to raise the voltage applied to the capacitive load from V1 to V2. When, subsequently, the voltage applied to the capacitive load is to be lowered from V2 to V1, the switch is again closed and the capacitive load allowed to discharge into the reserve capacitor to rapidly lower the voltage applied to the capacitive load.
In another embodiment, as described above, the driver further includes a second switch for electrically isolating the capacitive load from the output of the load buffer, and the method involves opening the second switch to electrically isolate the capacitive load from the output of the load buffer. Desirably, the second switch is opened at the same time, or shortly before, the first switch is closed to couple the reserve capacitor to the capacitive load.
In yet another aspect, the invention is directed to a non-volatile memory system for storing information therein. The memory system includes a number of storage elements or cells having a number of Field Effect Transistors (FETs) with gates electrically isolated from sources and drains of the FETs, and a driver coupled to the gates to simultaneously drive the gates of the number of FETs between a verify voltage (V1) and a programming voltage (V2). The driver has a load buffer with an input adapted to receive an input voltage (VIN), and an output adapted to couple an output voltage (VOUT) to the gates, and means for reducing time for VOUT to transition between V1 and V2. The load buffer is configured to drive VOUT between V1 and V2 in response to a change in VIN. Generally, the means for reducing time for VOUT to transition between V1 and V2 includes reserve circuit having a reserve capacitor, a reserve buffer having an input adapted to receive an input voltage (VRESxe2x80x94IN), and an output adapted to couple an output voltage (VRESxe2x80x94OUT) to the reserve capacitor to charge the reserve capacitor, a switch for coupling the reserve capacitor to the gates, and a controller for opening and closing the switch, the controller configured to operate the switch to couple the reserve capacitor to the gates when VOUT is being driven between V1 and V2.
In one embodiment, the memory system further includes a high-voltage-pump to supply voltage to the load buffer and the reserve buffer. Desirably, the storage elements, the driver and the high-voltage-pump are fabricated on a single substrate.
The advantages of the present invention include: (i) faster response time, (ii) efficient use of available power with substantially no increase in peak voltage needed from the existing high-voltage-pump, (iii) complete integration of driver including the reserve circuit onto a single substrate and (iv) reduced noise in the high-voltage-pump due to a steady, balanced consumption of current without any of the sharp increases or decreases that occur in prior art approaches.